Method of providing integrated diffused emitter ballast resistors for improved power capabilities of semiconductor devices

ABSTRACT

The disclosure is directed to planar transistors which include an emitter region disposed in a base region, the emitter region comprising an elongated spine from which spaced parallel emitter stripes project. The emitter electrode comprises a spine contact and individual electrode strips extending from the distal ends of the emitter fingers to locations spaced apart from the spine contact leaving discontinuities in the emitter electrode such that the sheet resistance of the emitter fingers underlying the discontinuities is utilized to form electrical ballast resistances in the emitter contact sufficient to prevent localized thermal runaway during operation of the transistor. The base contact has contact strips interdigitating with the emitter contact strips and extending from a common base electrode portion. Adjacent the discontinuities in the emitter contact, webs of emitter region material extend across the ends of the base contact strips and join adjacent ones of the emitter fingers to prevent deleterious localized current injection during operation of the transistor. An embodiment is also described in which the emitter region does not have a spine but consists of a series of spaced-apart, parallel extending fingers.

United States Patent [72] Inventor Ian Ihmbry Morgan Eaton Socon, St.Neots, England [21] Appl. No. 879,] 19

[22] Filed Nov. 24, 1969 l [45] Patented Nov. 9, I971 [73] AssigneeTexas Instruments Incorporated Dallas, Tex.

[54] METHOD OF PROVIDING INTEGRATED DIFFUSED EMITTER BALLAST RESISTORSFOR IMPROVED POWER CAPABILITIES 0F SEMICONDUCTOR DEVICES 7 Claims, 14Drawing Figs.

[52] US. Cl 317/235 R,

[51] Int. Cl H011 11/06 [50] Field of 317/235 [56] References CitedUNITED STATES PATENTS 3,225,261 12/1965 Wolf 317/235 3,358,197 12/1967Scarlett 317/235 3,444,443 5/1969 Moroshima llll 3,619,741

Primary Examiner-Jerry D. Craig Attorneys-James 0. Dixon, Andrew M.Hassell, Mel Sharp,

Harold Levine, John E. .Vandigrifi, Henry T. Olsen, Michael A. Sileo,Jr. and Gary C. Honeycutt ABSTRACT: The disclosure is directed to planartransistors which include an emitter region disposed in a base region,the emitter region comprising an elongated spine from which spacedparallel emitter stripes project. The emitter electrode comprises aspine contact and individual electrode strips extending from the distalends of the emitter fingers to locations spaced apart from the spinecontact leaving discontinuities in the emitter electrode such that thesheet resistance of the emitter fingers underlying the discontinuitiesis utilized to form electrical ballast resistances in the emittercontact sufficient to prevent localized thermal runaway during operationof the transistor. The base contact has contact strips interdigitatingwith the emitter contact strips and extending from a common baseelectrode portion. Adjacent the discontinuities in the emitter contact,webs of emitter region material extend across the ends of the basecontact strips and join adjacent ones of the emitter fingers to preventdeleterious localized current injection during operation of thetransistor. An embodiment is also described in which the emitter regiondoes not have a spine but consists of a series of spaced-apart, parallelextending fingers.

SHEET 2 BF 3 BEST WORST SAMPLE IO V 0 2 E C V l I I8 24 6/ TYPICALUNBALLASTED f= I75 MH \INSTABILITY AND P (WATTS DC) T B l 5 O 5 MS l I.

LRMmT 65551 n.

5.50m MT mmw m OMTF 88 7 MOE MV 1 WM l WLGOH w m O AT4 c l- 8 2 6 O I AC I. I Rfv SEE w om 1 W 0 T T S S R 2 E W S B W T M m T A W T m 11 P w14 m P 2 O 0 O O O 3 2 .l 0 .r30 1 fiwktiz m I S v T I T A W W P 8 aPATENTEDNDV 91911 3.619.741

SHEET 3 BF 3 M a a METHOD OF PROVIDING INTEGRATED DIFF USED EMITTERBALLAST RESISTORS FOR IMPROVED POWER CAPABILITIES OF SEMICONDUCTORDEVICES This invention relates to semiconductor devices, and moreparticularly, to transistors suitable for high power operations whilstremaining thennally stable, for example, as RF amplifiers or oscillatorsor current-switching devices. The invention is applicable both todiscrete semiconductor devices as well as to semiconductor devices whichare formed as elements of an integrated circuit, monolithic or hybrid.

Limitations have heretofore existed in the power-handling capabilitiesof transistors and in particular, the capabilities of power transistorsused at radio frequencies, wherein mismatch on tuning must be withstood.A substantial amount of these limitations have been due to secondarybreakdown caused by lateral thermal instability resulting from localizedthermal runaway. This thermal instability has been caused by largepositive temperature coefiicient of current flow in the transistor,wherein any slight nonuniformity of the transistor tends to cause anonuniform thermal distribution across the transistor upon theapplication of substantial power. Increased current flow through thetransistor then tends to take place in the hottest region of thetransistor, thereby causing further localized heating. A regenerativeeffect, termed localized thermal runaway in this description, may thusoccur, leading to catastrophic failure of the transistor.

It has heretofore been proposed to utilize a resistance having apositive temperature coefficient between the emitter contact and theemitter region of a transistor in order to thermally stabilize thetransistor and to reduce the tendency to lateral thermal instability ofthe transistor. For example, U.S. Pat. No. 3,286,138 issued Nov. l5,1966 to W. Shockley, discloses the provision of a layer of resistivemetal between the emitter region of a transistor and the metal emittercontact to thermally stabilize the transistor. This technique hasprovided improved thermal stability for transistors but has been foundto require a substantial amount of extra metallization, therebyresulting in increased production costs and sometimes presenting yieldproblems due to scratches and imperfections in the additionalmetallization layer. Moreover, such techniques have not been generallysatisfactory for use with transistors employing interdigitated geometryand intended for operation at high input frequencies. Techniques havealso been proposed for increasing the power handling capability ofinterdigitated transistors by controlling the contact geometry upon theemitter fingers but problems such as voltage differences along thefinger lengths have rendered such techniques generally impracticable.Another proposal has been the formation of resistive elements fromcontact metallization or by an additional metallization uponinterdigitated transistors by forming a number of thin film resistorsconnected in series to groups of emitter fingers, but problems havearisen due to lack of adequate control of the metallization thicknessand geometry as well as due to such phenomena as electromigration.

U.S. Pat. No. 3,358,197 issued Dec. I2, 1967 to M. Scarlett, discloses atransistor having an emitter region comprising a plurality of fingersextending from a common emitter portion, the emitter being formed in abase region which has an area of increased depth underlying the commonemitter portion. The emitter contact system comprises metallizationstrips overlying the outer portions of the emitter fingers and spacedfrom a contact portion to the common emitter portion so that the sheetresistance of the emitter region in the said spaces effectivelyintroduce series resistors between the emitter contact strips and thecommon emitter contact portion. This approach offers the prospect ofadvantages over the techniques discussed above but is liable to sufferfrom deleterious localized current injection from the emitter regionwherein the resistive element is formed and from that part of theemitter re gion to which external contact is made. The formation of thebase region with a portion of increased depth may also give rise toproduction yield problems and although this relatively deep portion ofthe base region is stated toprovide a relatively inactive portion of theemitter base junction, the result is effectively that of a low gaintransistor permanently in parallel with the transistor incorporating theactive regions of the emitter-base junctions.

The present invention constitutes an improvement over the abovedescribed prior proposals and provides a transistor device including anemitter region disposed in a base region, the emitter region havingindividual spaced-apart portions with portions of said base regioninterposed therebetween. An emitter electrode system isohmicallyconnected to and distributed over the said emitter region and includes aportion commonto all said individual emitter portions anddiscontinuities formed in the electrode system overareas of theindividual emitter portions to form electrical resistances suffcient tostabilize the current density of the device, thereby to preventlocalized thermal runaway. The device. also includes means for reducinglocalized current injection from parts of the emitter region adjacentsaid common portion of the emitter contact means into the base region.Preferably, the said electrical resistances are formed by the sheetresistance of the emitter region underlying the said discontinuities. Inparticular, the means for reducing localized current injection compriseswebs of emitter region material extending between and connectingadjacent ones of the individual emitter portions in the regions of thesaid discontinuities, the said webs extending across the ends of basecontact fingers located between the individual emitter portions. Suchwebs prevent localized current injection from undesired regions andsuppress any possible undesirable secondary transistor action. Byemployment of the invention, practicable transistors can be realizedwhich are capable of operation at high frequencies and withenha'ncedfreedom from thermal runaway, without employment of additional ormodified diffusion processes during fabrication of such transistors.

For a more complete understanding ofthe present invention and forfurther objects and advantages thereof, reference is now to thefollowing description taken in conjunction with the accompanyingdrawings, in which:

FIG. I is a top view of an embodiment of a transistor according to theinvention; a

FIG. 2 is a crosssectional view taken generally along the section lines2-2 of FIG. 1;

FIG. 3 is a cross-sectional view taken generally along the section lines33 of FIG. 1;

FIG. 4 is a diagrammatic illustrationof the geometry of a portion of thedevice shown in FIG. 1;

FIGS. 5 and 6 are schematic diagrams of equivalent circuits oftransistor constructions illustrating the improvements pro vided by thepresent invention;

FIGS. 7-l0 are graphs illustrating various operating parameters oftransistors embodying the invention; and

FIGS. [1-14 illustrate modifications of the transistor structure shownin FIG. 1.

FIGS. 1-3 show portions of a planar transistor employing a suitablesemiconductor material, e.g. silicon or germanium, and embodying thepresent invention. The construction of an NPNtransistor will bedescribed by way of example and it will be understood thePNP-transistors embodying the invention also may be constructed.

The transistor illustrated comprises a semiconductor body having anN-type collector region 10 formed therein. The collector region may, forexample, be a diffused region or an epitaxial region e.g. an N-typeepitaxial layer on an N+ type substrate. Using oxide masking anddiffusion techniques, a P- type base region 11 of uniform depth orthickness is inset in the collector region and an N-type emitter region12 is inset in the base region. The basecollector and base-emitterjunctions extend to a common surface of the semiconductor body and arethere covered by a protective passivating layer I3. e.g. a siliconoxide. The emitter region 12 is comblike in structure and comprises anelongated spine portion l4 having at plurality of spaced apart, parallelemitter stripes. such as l5.-lprojecting transversely therefrom.

An ohmic contact to the base region comprises a base contact spine 16parallel to the emitter spine 14 and spaced from the distal ends of theemitter stripes 15 with base contact fingers such as l7a-c extendingfrom the spine 16 between the emitter stripes 15 towards the emitterspine 14 and in ohmic contact with underlying stripes 18 of the baseregion. It is to be noted that the base contact fingers l7 terminatewell short of the junction between the base region stripes l8 and theemitter spine 14 to reduce localized injection.

An emitter contact system 19 has an emitter contact spine 20 extendingalong and in ohmic contact with the emitter spine 14 and emitter contactfingers such as 2la-c overlying and in ohmic contact with portions ofthe emitter stripes la-c. The emitter contact fingers 2lA-c extend fromthe distal ends of the emitter stripes l5a-c towards the emitter contactspine 20, interdigitating with the base contact fingers l7a-c, and animportant feature of the invention is spaces or discontinuities 22a-c inthe emitter contact system between the emitter contact spine and thecontact fingers.

The emitter and base contacts ohmically contact the respective emitterand base regions through appropriate apertures in the oxide layer 13 andpreferably, as shown in FIGS. 2 and 3, extend out from the aperturesover part of the oxide layer. These ohmic contacts can be formed byselectively etching a metallization layer fon'ned on the oxide layer.This layer may comprise a single metallurgical component e.g. aluminumor may be of multiple layer metallurgy having two or more componentse.g. molybdenum overlaid by gold or aluminum; or gold sandwiched betweenlayers of molybdenum and in such cases the underlying layer ofmolybdenum may itself be attached to the semiconductor by an by aninterposed thin layer of aluminum. An ohmic contact (not shown) to thecollector region may be formed in like manner.

As noted above, an important feature of the invention is the formationof the discontinuities 22a-c in the emitter contact system whereby theareas of semiconductor material of the emitter region underlying thediscontinuities, provide sheet resistances of sufficient magnitude toimpart thermal stability to the transistor during operation thereof.Electrically these resistances are in series between the emitter contactspine 20 and the emitter contact fingers 210-0 and current between thecontact spine 20 and the fingers 2la-c flows through the sheetresistances provided by areas of the emitter stripes l5 underlying thediscontinuities. It may be noted that:

s s P( ns)/ q (minus the bandgap potenwherein,

R the value of the resistive element.

The interdigitated transistor of FIGS. l-3 provides advantages in theratio of emitter periphery to base area, which is a major factor ingoverning current handling capability, particularly when utilized in RFenvironments. Reduced capacitance values are also provided by theinterdigitated transistor. The resistive areas formed by thediscontinuities 22a-c may be very accurately defined by the conventionalphotomasking techniques.

The use of an emitter spine results in improved yield and reliabilitysince, by comparison with construction not using such a spine, thecurrent density within the emitter contact 19 is reduced on crossing thediscontinuity, formed at the edge of the contact aperture, to thesemiconductor material.

FIG. 4 diagrammatically illustrates the geometry for the computation ofthe resistance formed by one of the discontinuities 22in the metalemitter electrode. The resistance may be defined as follows:

I) a) a i 12- (3) wherein,

pSE the sheet resistance of the diffused emitter region, d the distancebetween the end of an emitter finger contact 21 and the emitter spinecontact 19,

a the width of the emitter finger contact 21,

b= the width of the base of a trapezoid drawn from the corners of theemitter finger contact 21 to the emitter spine contact 19 and passingthrough the corners of the junction between the emitter stripe l5 andthe emitter spine 14.

It will thus be seen that the resistance formed between each of theemitter contact fingers Zla-c and the emitter contact spine 19 comprisesa trapezoidal spreading resistance. Spreading resistances may thus bevery accurately determined for a given value of emitter sheet resistanceby suitably controlling the geometric parameters a, b, and d accordingto Equation 3. In practice, the resistance defined in Equation 3 may beslightly lower than the defined trapezoidal value, due to spreading inthe difiused emitter sheet.

The use of an emitter spine and the consequent trapezoidal spreadingresistance results in less variation in resistance value due togeometric variance in processing than can be achieved in a constructionnot incorporating such a spine and having a rectalinear spreadingresistance.

In practical embodiments of the present interdigitated transistor, asheet resistance value of about 5 ohms formed by a discontinuity in eachemitter contact strip has been found to work well, but of course, suchresistances may be widely varied for different applications. Inpractical manufacture of the devices, some variances in the photoresisttechniques may cause slight variations in the specified geometry of thediscontinuities. However, such variations have not been found tosubstantially affect the operation of the transistors, due to the factthat the variances in the final sheet resistance are generallynegligible.

The present invention not only provides operational advantages due tothe ballasting of individual emitter fingers, but also enables wafersizes to be reduced by as much as about one-third. The present inventionthus makes it possible to increase the overload capability for aninterdigitated transistor, in addition to increasing the collectorefficiency and increasing the power gain at high input powers.

As a result of the manner of geometric delineation of the resistiveelement in each emitter finger, the resistor value may be readilyincreased such that improved resistance to thermal instability isobtained at the expense of power gain, which is then lowered due todegeneration as a result of increasing the total resistance in theemitter terminal.

The transistor shown in FIGS. 1-3 also includes diffused webs, or falsespines, 230-0 of emitter semiconductor material which are formed acrossthe ends of the base contact fingers l8a-c adjacent the ends of theemitter contact fingers 2la-c, to reduce localized current injection dueto the proximity of the base contact fingers to the emitter spine 14.Portions 24a-c of base region semiconductor material are thus interposedbetween the webs 23a-c and the emitter spine 14. The ends of the webs23a-c are integral with and connect adjacent ones of the emitter fingersISa-c. The oxide layer 13 covers the upper surfaces of the webs 23a-cand the base portions 24a-c as shown in FIG. 3. The emitter webs 23acare preferably of narrower width than the width of the emitter fingetsand, as shown in FIG. 3, are not necessarily contacted by the emitterstripe metallization.

In operation of a particular embodiment of the transistor described withreference to FIGS. 1-3, but in the absence of the emitter webs 23a-c,voltage drops of about 100-300 millivolts typically may occur across theemitter ballast resistors provided by the regions 22a-c. Due to therelationship shown by equation 1, localized current injection may takeplace from the emitter spine directly opposite the ends of the basecontact fingers. This localized injection may lead to possible failureof the transistor, or of degradation of current dependent operatingparameters such as h or it This problem may be further understood byreference to FIG. 5 wherein an equivalent circuit approximating atransistor as shown in FIGS. 1-3, but not incorporating the emitter webs23a-c, is illustrated. A large area transistor designated generally bythe reference 40 represents the ballasted emitter fingers with a smallarea transistor designated generally by the reference 42 representingthe regions opposite the ends of the base contact finger capable ofoperating with high bias V The emitters of transistors 40 and 42 areconnected to a resistance 44, which is representative of the magnitudeof the resistances formed by the sheet resistance of the portions 22a-cof the diffused emitter regions. The bases and collectors of transistors40 and 42 are commonly connected. It will thus be understood that theproperties of the transistors 40 and 42 primarily depend upon the valueof current flowing through the small area transistor 42.

In operation of the transistor described with reference to FIGS. 1-3,and which does include the emitter web portions 23a-c, the emitter websare at the same potential as the adjacent ends of the emitter stripesi.e. the potential at the active or emitter stripe ends of the ballastresistors. The emitter spine edge is at a higher potential than that atthe "active" ends of the ballast resistors and since the high potentialemitter spine edge is essentially screened by the webs 23a-c, thecurrent injection from the spine due to the base contact finger ends,and the secondary low gain transistor action from the spine region, areeliminated. The screening action is caused at a normal current level dueto the fact that current crowding causes the injected emitter current tobe localized at the web edge adjacent the ends of the base contactfingers 17. This injected emitter current effectively forms arecombination barrier that prevents base current from reaching the highpotential emitter spine edge. Essentially, a controlled amount ofcurrent injection is thus caused immediately adjacent the base contactfinger ends, thereby preventing interaction with the higher potentialregion of the emitter spine contact.

The schematic equivalent circuit of the transistor is then changed fromthe parallel transistor combination shown in FIG. 5 to the multiemittersingle transistor configuration indicated in FIG. 6. Although aresistance 50 of about 5 ohms may be inserted in each emitter contactfinger, FIG. 6 indicates that the total resistance in the emitter leadliable to cause degradation of power gain is inversely proportional tothe number of emitter stripes incorporated in the transistor.

FIG. 7 is a plot of the active region temperature Tj (as measured at theemitter-base junction) above ambient against DC power dissipation P andillustrates the improved power capacity of a typical transistorembodying the invention. Curve 60 illustrates a capacity approximating30 watts of DC power over a temperature range of 200 C. above ambienttemperature without failure of the transistor. As shown in this graph,this perfonnance is superior to that of various otherwise comparable,conventional unballasted transistors, the limits of operation of which(indicated by instability and hotspot formation) fall over the indicatedrange A. This performance is also superior to that of otherwisecomparable transistors having aluminum metal resistors each in serieswith a group of emitters; in the example illustrated, 0.5 ohm resistorsin series with emitter contact fingers, wherein the maximum powerdissipation at the limits of operation fall over the range 8 i.e. amaximum power dissipation of about 10 watts.

FIGS. 8-10 illustrate the power gain of typical interdigitatedtransistors embodying the present invention. FIG. 8 is a plot of outputpower versus input power and shows the performance spread of a batch of25 transistors operated at about 400 MHz with a V of 28 volts. FIG. 9 isa plot of output power versus input power and shows the performancespread of a batch of [0 transistors operated at about I75 MHz and with aV of about 28 volts, while FIG. 10 shows the performance spread of abatch of 12 transistors operated at the same frequency with a V of 13volts. In FIG. 9, the broken line 61 indicates the input and outputpowers at which a batch otherwise comparable, typical conventionalunballasted transistors were subject to catastrophic failure due tothermal instability. In FIGS. 8-10, it may be seen that the best andworst cases of the transistor groups, embodying the invention, areextremely closely spaced, thereby illustrating not only the excellentperformance of the present transistors but also the manufacturingreliability possible of the result of this invention.

The improved power dissipation properties of transistors embodying theinvention indicate that a large degree of mismatch under operationalconditions may be tolerated with impunity.

Although the present invention has been described with reference tospecific embodiments thereof, it will be understood that various changesand modifications may become apparent to one skilled in the art,examples of some posible modifications being illustrated in FIGS. ll-l4.

FIG. 11 illustrates a transistor having a base region in which are insettwo spaced emitter spines 14, each having emitter fingers such as ISa-cextending transversely therefrom, the emitter spines extending parallelto one another and being disposed back-to-back. The formation of theemitter contact fingers 21, the discontinuities 224-1: and the emitterwebs 23a-c is identical in each case to that described with reference toFIGS. 1-3. However, both sets of emitter contact fingers 21, areassociated with a common emitter contact spine 25.

In FIG. 12, there is shown a modification of the structure of FIGS. 1-3,suitable for use in transistors intended for lowfrequency operation. Inlow-frequency transistors, the sheet resistance of the emitter region,used in accordance with the invention to provide the emitter ballastresistors, may be relatively low and in order to maintain tolerancecompatibility, the width of the regions 22 of the emitter stripes I5 isreduced as compared with the width of the remainder of the emitterstripes, in order to provide the required resistance value.

When transistor intended for operation is in the region of the upperlimit of high frequency that can be attained at the present state of theart, the emitter region has a high sheet resistance and, again in orderto maintain tolerance compatibility, the width of the regions 22 may beincreased compared to the width of the remainder of the emitter stripesto obtain the required resistance value, as illustrated in FIG. 13.

Apart from the changes described, the structures of the embodimentsillustrated by FIGS. 12 and 13 is the same as that described withreference to FIGS. 1-3 and like references have been used whereappropriate.

In all the above described embodiments of the invention, the emitterregion of the transistor is comprised of spaced fingers projecting froman emitter spine to form a comblike structure. However, it will beappreciated that other geometries e. g. a rib and spine or star-shaped,also may be employed. Further, it is not an essential feature of theinvention that an emitter spine or common portion be employed andembodiments of the invention may be instructed incorporating discrete,spaced emitter regions. One such embodiment is shown in FIG. 14, thelaterally spaced emitter fingers l5a-c being joined towards one endthereof by transversely extending emitter webs 23a-c. At that end of theemitter stripes, an elongated metal contact pad 27 extends parallel to,and spaced from, the emitter webs 23a-c over the emitter fingers, makingohmic contact with each of them through apertures 28 in the oxide layer.Alternatively, the contact pad may be on the oxide over the collectorregion and metal fingers projecting from the contact pad extend over theoxide step at the base-collector junction to contact the emitter fingersthrough the apertures 28. The emitter stripes ISa-c have respectivecontact fingers Zla-c which terminate adjacent the emitter webs 2311-1:so that, as in the previously described embodiments, the sheetresistance of the emitter regions at the discontinuities 22a-c formresistances in series between each emitter contact finger and thecontact pad 27. in other respects, the structure of the embodiment shownin FIG. 14 remains unchanged from that described with reference to FIGS.1-3.

The features of the above described embodiments of the invention may beutilized in the manufacture of discrete devices and also of transistorsformed as circuit elements in monolithic and hybrid integrated circuits.

What is claimed is:

1. A planar transistor including a base region of one conductivity typeand an emitter region of opposite type inset in the base region, theemitter region comprising a common portion having spaced elongatedportions projecting therefrom, a base electrode comprising electrodestrips extending between said elongated emitter portions from a commonbase electrode portion, an emitter electrode system comprising anelectrode portion on the said common emitter portion and electrodestrips on the respective elongated emitter portions terminating short ofthe common emitter electrode portion whereby the sheet resistance of theelongated emitter portions not overlaid by said electrode strips provideseries resistances between said common emitter electrode portions andsaid emitter electrode strips, and wherein webs of emitter materialextend between and interconnect adjacent elongated emitter portions, thesaid webs being located between the ends of the base electrode stripsand said common emitter portion in the vicinities of the ends of theemitter electrode strips adjacent the common emitter portion.

2. The planar transistor of claim 1, wherein the emitter regioncomprises an elongated common spine portion and spaced parallel emitterstripes projecting therefrom.

3. A planar transistor including a base region of one conductivity typeand discrete, spaced elongated emitter portions of opposite conductivitytype inset in the base region, a base electrode having electrode stripsextending between the said emitter portions from a common base contactportion, an emitter electrode system comprising a common portionohmically connected to each of said emitter portions and emitterelectrode strips overlying parts of the respective emitter portions andextending towards but spaced from the said common emitter electrodeportion to leave an area of each emitter portion disposed between theelectrode strip of that emitter porto the said common emitter electrodeportion by series resistances formed by the sheet resistance of the saidareas of the emitter portions, and wherein webs of emitter materialextend between and interconnect adjacent emitter portions, the said websbeing located between the ends of the base electrode strips and thecommon emitter contact portion in the vicinities of the terminations ofthe emitter electrode strips at said areas of the emitter portions.

4. the planar transistor of claim 3, wherein the emitter portions areparallel, spaced elongated portions ohmically interconnected at one endby a transversely extending common emitter electrode portion, whereinsaid emitter electrode strips extend from the opposite ends of saidemitter portions to locations in the vicinity of said webs of emittermaterial.

5. A transistor device including emitter and base regions with aPN-junction therebetween, said emitter region including a common regionfrom which individual spaced-apart portions project, said spaced-apartportions being disposed in the base region so that portions of the baseregion are interposed between said individual emitter portions; emitterelectrode means ohmically connected to and distributed over said emitterregions, a portion of said electrode means being common to all saidindividual emitter portions, with discontinuities formed in saidelectrode means over areas of the said individual emitter portions toform electrical resistances sufficient to stabilize the current densityof the device, thereby to prevent localized thennal runaway; and webs ofmaterial of said emitter region extending between and joining adjacentones of said spaced emitter portions for screening said interposedportions of said base region from electrical potential appearing on saidcommon emitter portion, whereby localized current injection is reducedfrom parts of said emitter region adjacent said common portion of theemitter contact means into said interposed portions of said base region.

6. The transistor device of claim 5, wherein said webs are disposedadjacent the junctures of said discontinuities and the electrode meansoverlying said individual emitter portions.

7. The transistor device of claim 5, wherein said common emitter portionis an elongated spine and said individual emitter portions are outwardlyprojecting stripes spaced along the length of said spine, saiddiscontinuities being formed in the area of the juncture of said spineand said emitter stripes such that the sheet resistances of portions ofsaid emitter stripes underlying the discontinuities form said electricalresistances.

1. A planar transistor including a base region of one conductivity typeand an emitter region of opposite type inset in the base region, theemitter region comprising a common portion having spaced elongatedportions projecting therefrom, a base electrode comprising electrodestrips extending between said elongated emitter portions from a commonbase electrode portion, an emitter electrode system comprising anelectrode portion on the said common emitter portion and electrodestrips on the respective elongated emitter portions terminating short ofthe common emitter electrode portion whereby the sheet resistance of theelongated emitter portions not overlaid by said electrode strips provideseries resistances between said common emitter electrode portions andsaid emitter electrode strips, and wherein webs of emitter materialextend between and interconnect adjacent elongated emitter portions, thesaid webs being located between the ends of the base electrode stripsand said common emitter portion in the vicinities of the ends of theemitter electrode strips adjacent the common emitter portion.
 2. Theplanar transistor of claim 1, wherein the emitter region comprises anelongated common spine portion and spaced parallel emitter stripesprojecting therefrom.
 3. A planar transistor including a base region ofone conductivity type and discrete, spaced elongated emitter portions ofopposite conductivity type inset in the base region, a base electrodehaving electrode strips extending between the said emitter portions froma common base contact portion, an emitter electrode system comprising acommon portion ohmically connected to each of said emitter portions andemitter electrode strips overlying parts of the respective emitterportions and extending towards but spaced from the said common emitterelectrode portion to leave an area of each emitter portion disposedbetween the electrode strip of that emitter portion and the commonemitter electrode portion whereby the emitter electrode strips areeffectively electrically connected to the said common emitter electrodeportion by series resistances formed by the sheet resistance of the saidareas of the emitter portions, and wherein webs of emitter materialextend between and interconnect adjacent emitter portions, the said websbeing located between the ends of the base electrode strips and thecommon emitter contact portion in the vicinities of the terminations ofthe emitter electrode strips at said areas of the emitter portions. 4.The planar transistor of claim 3, wherein the emitter portions areparallel, spaced elongated portions ohmically interconnected at one endby a transversely extending common emitter electrode portion, whereinsaid emitter electrode strips extend from the opposite ends of saidemitter portions to locations in the vicinity of said webs of emittermaterial.
 5. A transistor device including emitter and base regions witha PN-junction therebetween, said emitter region including a commonregion from which individual spaced-apart portions project, saidspaced-apart portions being disposed in the base region so that portionsof the base region are interposed between said individual emitterportions; emitter electrode means ohmically connected to and distributedover said emitter regions, a portion of said electrode means beingcommon to all said individual emitter portions, with discontinuitiesformed in said electrode means over areas of the said individual emitterportions to form electrical resistances sufficient to stabilize thecurrent density of the device, thereby to prevent localized thermalrunaway; and webs of material of said emitter region extending betweenand joining adjacent ones of said spaced emitter portions for screeningsaid interposed portionS of said base region from electrical potentialappearing on said common emitter portion, whereby localized currentinjection is reduced from parts of said emitter region adjacent saidcommon portion of the emitter contact means into said interposedportions of said base region.
 6. The transistor device of claim 5,wherein said webs are disposed adjacent the junctures of saiddiscontinuities and the electrode means overlying said individualemitter portions.
 7. The transistor device of claim 5, wherein saidcommon emitter portion is an elongated spine and said individual emitterportions are outwardly projecting stripes spaced along the length ofsaid spine, said discontinuities being formed in the area of thejuncture of said spine and said emitter stripes such that the sheetresistances of portions of said emitter stripes underlying thediscontinuities form said electrical resistances.